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authorYann Herklotz Grave <git@yannherklotzgrave.com>2019-02-16 14:43:47 +0000
committerYann Herklotz Grave <git@yannherklotzgrave.com>2019-02-16 14:43:47 +0000
commita180c89947f8e0c191ba7e7dba4c6eb7edf538e6 (patch)
treee208bfc464e926bcdcccc614a0c27324b1bede26 /src/VeriFuzz/Mutate.hs
parent5cee65b1d5e56573204217a800ad04d7209313dd (diff)
downloadverismith-a180c89947f8e0c191ba7e7dba4c6eb7edf538e6.tar.gz
verismith-a180c89947f8e0c191ba7e7dba4c6eb7edf538e6.zip
Fix lint errors
Diffstat (limited to 'src/VeriFuzz/Mutate.hs')
-rw-r--r--src/VeriFuzz/Mutate.hs12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs
index 56db6c4..b8b1f59 100644
--- a/src/VeriFuzz/Mutate.hs
+++ b/src/VeriFuzz/Mutate.hs
@@ -128,8 +128,8 @@ instantiateModSpec_ outChar m = ModInst (m ^. modId) (m ^. modId) conns
where
conns =
zipWith ModConnNamed ids (Id <$> instIds)
- ids = (filterChar outChar $ name modOutPorts) ++ (name modInPorts)
- instIds = (name modOutPorts) ++ (name modInPorts)
+ ids = filterChar outChar (name modOutPorts) <> name modInPorts
+ instIds = name modOutPorts <> name modInPorts
name v = m ^.. v . traverse . portName
filterChar :: Text -> [Identifier] -> [Identifier]
@@ -172,7 +172,7 @@ makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop 2
assert = Always . EventCtrl e . Just $ SeqBlock
[TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]]
e = EPosEdge "clk"
- addClk = ((Port Wire 1 "clk") :)
+ addClk = (Port Wire 1 "clk" :)
-- | Provide declarations for all the ports that are passed to it.
declareMod :: [Port] -> ModDecl -> ModDecl
@@ -222,10 +222,10 @@ simplify e = e
-- >>> GenVerilog . removeId ["x"] $ Id "x" + Id "y"
-- (x + (-1'h0))
removeId :: [Identifier] -> Expr -> Expr
-removeId i expr =
- transform trans expr
+removeId i =
+ transform trans
where
trans (Id ident)
- | all (ident /=) i = Number 1 0
+ | ident `notElem` i = Number 1 0
| otherwise = Id ident
trans e = e