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| author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 20:22:29 +0000 |
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| committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 20:22:29 +0000 |
| commit | d0dd067977e9e6db748dfc894ebde13d3c58e525 (patch) | |
| tree | 3ab68ff2a8be0e9d50ef63cce26d1af8a49c2db5 /src/VeriFuzz/Mutate.hs | |
| parent | 5025a43948a682bc40d5c91606ec97cd8d6c3897 (diff) | |
| download | verismith-d0dd067977e9e6db748dfc894ebde13d3c58e525.tar.gz verismith-d0dd067977e9e6db748dfc894ebde13d3c58e525.zip | |
Change to Parsec and add Lexer
Diffstat (limited to 'src/VeriFuzz/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Mutate.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Mutate.hs b/src/VeriFuzz/Mutate.hs index 15eac90..21911b6 100644 --- a/src/VeriFuzz/Mutate.hs +++ b/src/VeriFuzz/Mutate.hs @@ -79,7 +79,7 @@ allVars m = -- $setup -- >>> import VeriFuzz.CodeGen --- >>> let m = (ModDecl (Identifier "m") [Port Wire 5 (Identifier "y")] [Port Wire 5 "x"] []) +-- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] []) -- >>> let main = (ModDecl "main" [] [] []) -- | Add a Module Instantiation using 'ModInst' from the first module passed to |