diff options
| author | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-10 23:42:58 +0100 |
| commit | 186bb5f37770c150bd8e601e9761211af6a9c277 (patch) | |
| tree | 33ccc13403d1c9a168909b1e9987f29028834396 /src/VeriFuzz/Sim/Icarus.hs | |
| parent | aefb46596f3f2302540a83b2be8b042232822a2f (diff) | |
| download | verismith-186bb5f37770c150bd8e601e9761211af6a9c277.tar.gz verismith-186bb5f37770c150bd8e601e9761211af6a9c277.zip | |
Fix the generation of modules and add initialisation
Diffstat (limited to 'src/VeriFuzz/Sim/Icarus.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Icarus.hs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs index 9b5138f..8876706 100644 --- a/src/VeriFuzz/Sim/Icarus.hs +++ b/src/VeriFuzz/Sim/Icarus.hs @@ -92,7 +92,8 @@ runSimIcarus sim rinfo bss = do [ Initial $ fold (addDisplay $ assignFunc (_modInPorts m) <$> bss) <> (SysTaskEnable $ Task "finish" []) - ] [] + ] + [] let newtb = instantiateMod m tb let modWithTb = Verilog [newtb, m] writefile "main.v" $ genSource modWithTb |