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| author | Yann Herklotz <git@ymhg.org> | 2019-04-21 07:19:06 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-21 07:19:06 +0100 |
| commit | 8f7d6e4ee2941c592a33510687a724c4c733d403 (patch) | |
| tree | 9b8555ff04b7981470362f7e89e4fde6c1f6a103 /src/VeriFuzz/Sim/Quartus.hs | |
| parent | 220ebcba740e128b0065facbdfd27682ad39e1dd (diff) | |
| download | verismith-8f7d6e4ee2941c592a33510687a724c4c733d403.tar.gz verismith-8f7d6e4ee2941c592a33510687a724c4c733d403.zip | |
Add new modules to fix Quartus equivalence check
Diffstat (limited to 'src/VeriFuzz/Sim/Quartus.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Quartus.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs index 5bda0be..cac1fb8 100644 --- a/src/VeriFuzz/Sim/Quartus.hs +++ b/src/VeriFuzz/Sim/Quartus.hs @@ -55,6 +55,7 @@ runSynthQuartus sim (SourceInfo top src) = do ex (exec "quartus_eda") [top, "--simulation", "--tool=vcs"] liftSh $ do cp (fromText "simulation/vcs" </> fromText top <.> "vo") $ synthOutput sim + run_ "sed" ["-ri", "s,^// DATE.*,,; s,^tri1 (.*);,wire \\1 = 1;,; /^\\/\\/ +synopsys/ d;", toTextIgnore $ synthOutput sim] echoP "Quartus synthesis done" where inpf = "rtl.v" |