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| author | Yann Herklotz <git@ymhg.org> | 2019-04-23 15:51:34 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-23 15:51:34 +0100 |
| commit | d13375f31f4c298a379ac3c17e7f81ea12e4312c (patch) | |
| tree | a6e88360593bfe999966b30eb62383026af9f5ef /src/VeriFuzz/Sim | |
| parent | 528395c067815474af4e9d850352a1332434a321 (diff) | |
| download | verismith-d13375f31f4c298a379ac3c17e7f81ea12e4312c.tar.gz verismith-d13375f31f4c298a379ac3c17e7f81ea12e4312c.zip | |
Fix some errors in the templates
Diffstat (limited to 'src/VeriFuzz/Sim')
| -rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 93f24a3..771646d 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -90,6 +90,7 @@ write_verilog -force #{outf} -- brittany-disable-next-binding sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> Maybe b -> SourceInfo -> Text sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options] +multiclock on mode prove [engines] |