diff options
| author | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:24 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:24 +0100 |
| commit | d695414e67f9adb7f665602a20a898fa77eba106 (patch) | |
| tree | d22e902e4e34b5c4385f0c863da6e71803903613 /src/VeriFuzz/Sim | |
| parent | e22a59ad643ac2fe96b0c11208651a6f7a6605b0 (diff) | |
| download | verismith-d695414e67f9adb7f665602a20a898fa77eba106.tar.gz verismith-d695414e67f9adb7f665602a20a898fa77eba106.zip | |
Change Port type to include lower bound
Diffstat (limited to 'src/VeriFuzz/Sim')
| -rw-r--r-- | src/VeriFuzz/Sim/Reduce.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs index 381a84c..361df3e 100644 --- a/src/VeriFuzz/Sim/Reduce.hs +++ b/src/VeriFuzz/Sim/Reduce.hs @@ -67,8 +67,8 @@ filterExpr ids (Id i) = if i `notElem` ids then Number 1 0 else Id i filterExpr _ e = e filterDecl :: [Identifier] -> ModItem -> Bool -filterDecl ids (Decl Nothing (Port _ _ _ i) _) = i `elem` ids -filterDecl _ _ = True +filterDecl ids (Decl Nothing (Port _ _ _ _ i) _) = i `elem` ids +filterDecl _ _ = True filterAssigns :: [Port] -> ModItem -> Bool filterAssigns out (ModCA (ContAssign i _)) = |