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| author | Yann Herklotz <git@ymhg.org> | 2019-05-10 17:41:44 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-10 17:41:44 +0100 |
| commit | 1bf5b56da8df267fd33e738b53e29e832854856b (patch) | |
| tree | 83b451ca816e9fffc3faadef3ed37054549820f6 /src/VeriFuzz/Verilog.hs | |
| parent | 8241ebad9374187b20ee0fdd43029a2a5ddfbb4e (diff) | |
| download | verismith-1bf5b56da8df267fd33e738b53e29e832854856b.tar.gz verismith-1bf5b56da8df267fd33e738b53e29e832854856b.zip | |
Add constant expression to expression conversion and vice versa
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index 4f9fd52..701a7d6 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -53,6 +53,8 @@ module VeriFuzz.Verilog -- * Expression , Expr(..) , ConstExpr(..) + , constToExpr + , exprToConst , constNum -- * Assignment , Assign(..) |