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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 17:46:56 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 17:46:56 +0000 |
commit | 3e37e75f804cbf6b5ce04a427888fb0f0859660a (patch) | |
tree | e0602c9777a36ad677009031cc8edaa5fefc22cd /src/VeriFuzz/Verilog/AST.hs | |
parent | 8a70b3fa892aaa095aa423609bfadaecea44c655 (diff) | |
download | verismith-3e37e75f804cbf6b5ce04a427888fb0f0859660a.tar.gz verismith-3e37e75f804cbf6b5ce04a427888fb0f0859660a.zip |
[Fix #22] Fix SAT solver equivalence checking
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index 1b2cb19..b02da1b 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -104,6 +104,8 @@ module VeriFuzz.Verilog.AST , declPort , ModConn(..) , modConn + , modConnName + , modExpr ) where @@ -398,11 +400,17 @@ instance QC.Arbitrary Port where -- @ -- mod a(.y(y1), .x1(x11), .x2(x22)); -- @ -newtype ModConn = ModConn { _modConn :: Expr } - deriving (Eq, Show, QC.Arbitrary) +data ModConn = ModConn { _modConn :: Expr } + | ModConnNamed { _modConnName :: Identifier + , _modExpr :: Expr + } + deriving (Eq, Show) makeLenses ''ModConn +instance QC.Arbitrary ModConn where + arbitrary = ModConn <$> QC.arbitrary + data Assign = Assign { _assignReg :: LVal , _assignDelay :: Maybe Delay , _assignExpr :: Expr |