diff options
| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:53:08 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:53:08 +0000 |
| commit | a27290529940e7a78dfe1d736447ca6f1cf72089 (patch) | |
| tree | 06c52149bbf2216fa02943dae0a4518749a372d0 /src/VeriFuzz/Verilog/AST.hs | |
| parent | 75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b (diff) | |
| download | verismith-a27290529940e7a78dfe1d736447ca6f1cf72089.tar.gz verismith-a27290529940e7a78dfe1d736447ca6f1cf72089.zip | |
Add hlint changes
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index dd61f03..9db4999 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -514,8 +514,7 @@ modPortGen = QC.oneof ] instance QC.Arbitrary ModDecl where - arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary - <*> QC.listOf1 modPortGen <*> QC.arbitrary + arbitrary = ModDecl <$> QC.arbitrary <*> QC.arbitrary <*> QC.listOf1 modPortGen <*> QC.arbitrary -- | Description of the Verilog module. newtype Description = Description { _getDescription :: ModDecl } |