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| author | Yann Herklotz <git@ymhg.org> | 2019-04-26 13:48:32 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-26 13:48:56 +0100 |
| commit | 1f92f329dabfaf5077bed677a273a196667229e1 (patch) | |
| tree | a19c9ed6ec91db71d51684911420fd12a80a59bc /src/VeriFuzz/Verilog/AST.hs | |
| parent | 1486a2afa481de46938c1bc122c469975978593f (diff) | |
| download | verismith-1f92f329dabfaf5077bed677a273a196667229e1.tar.gz verismith-1f92f329dabfaf5077bed677a273a196667229e1.zip | |
Add random bit selection for wires
This has not been tested fully yet
Diffstat (limited to 'src/VeriFuzz/Verilog/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/AST.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/AST.hs b/src/VeriFuzz/Verilog/AST.hs index f122214..ea7ef1b 100644 --- a/src/VeriFuzz/Verilog/AST.hs +++ b/src/VeriFuzz/Verilog/AST.hs @@ -209,6 +209,8 @@ data UnaryOperator = UnPlus -- ^ @+@ data Expr = Number {-# UNPACK #-} !BitVec -- ^ Number implementation containing the size and the value itself | Id {-# UNPACK #-} !Identifier + | VecSelect {-# UNPACK #-} !Identifier !Expr + | RangeSelect {-# UNPACK #-} !Identifier !Range -- ^ Symbols | Concat ![Expr] -- ^ Bit-wise concatenation of expressions represented by braces. |