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author | Yann Herklotz <git@ymhg.org> | 2019-05-11 22:14:42 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-05-11 22:14:42 +0100 |
commit | 9637980a562d79582689daa5dff43814a531f900 (patch) | |
tree | 311fba411d26af930b1662f42c9648a48326c2d5 /src/VeriFuzz/Verilog/CodeGen.hs | |
parent | 6218c8fd0f7dae36bda08fd2b132901e4707584a (diff) | |
download | verismith-9637980a562d79582689daa5dff43814a531f900.tar.gz verismith-9637980a562d79582689daa5dff43814a531f900.zip |
Implement module item reduction properly
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
-rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index efacd3c..71ba162 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -11,7 +11,8 @@ This module generates the code from the Verilog AST defined in "VeriFuzz.Verilog.AST". -} -{-# LANGUAGE FlexibleInstances #-} +{-# LANGUAGE DeriveDataTypeable #-} +{-# LANGUAGE FlexibleInstances #-} module VeriFuzz.Verilog.CodeGen ( -- * Code Generation @@ -21,6 +22,7 @@ module VeriFuzz.Verilog.CodeGen ) where +import Data.Data (Data) import Data.List.NonEmpty (NonEmpty (..), toList) import Data.Text (Text) import qualified Data.Text as T @@ -318,6 +320,7 @@ instance Source SourceInfo where genSource (SourceInfo _ src) = genSource src newtype GenVerilog a = GenVerilog { unGenVerilog :: a } + deriving (Eq, Ord, Data) instance (Source a) => Show (GenVerilog a) where show = T.unpack . genSource . unGenVerilog |