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| author | Yann Herklotz <git@ymhg.org> | 2019-04-04 15:30:52 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-04 15:30:52 +0100 |
| commit | b4b1d0dcb0864c25275fdcc1ccd93a4dfaae51a1 (patch) | |
| tree | 40ee3f86bd2bb35bc43e33ed702a4c5595f1ef5f /src/VeriFuzz/Verilog/CodeGen.hs | |
| parent | 855cae6758b4dd92280d7548862b3d9c8cf61281 (diff) | |
| download | verismith-b4b1d0dcb0864c25275fdcc1ccd93a4dfaae51a1.tar.gz verismith-b4b1d0dcb0864c25275fdcc1ccd93a4dfaae51a1.zip | |
Better formatting for if-statement
Diffstat (limited to 'src/VeriFuzz/Verilog/CodeGen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/CodeGen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/CodeGen.hs b/src/VeriFuzz/Verilog/CodeGen.hs index eb3b3d1..a05309f 100644 --- a/src/VeriFuzz/Verilog/CodeGen.hs +++ b/src/VeriFuzz/Verilog/CodeGen.hs @@ -215,9 +215,9 @@ statement (NonBlockAssign a ) = genAssign " <= " a <> ";\n" statement (StatCA a ) = contAssign a statement (TaskEnable t ) = task t <> ";\n" statement (SysTaskEnable t ) = "$" <> task t <> ";\n" -statement (CondStmnt e t Nothing) = "if(" <> expr e <> ")" <> defMap t +statement (CondStmnt e t Nothing) = "if(" <> expr e <> ")\n" <> defMap t statement (CondStmnt e t f) = - "if(" <> expr e <> ") " <> defMap t <> "else " <> defMap f + "if(" <> expr e <> ")\n" <> defMap t <> "else\n" <> defMap f task :: Task -> Text task (Task name e) | null e = i |