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authorYann Herklotz <git@ymhg.org>2019-04-17 19:20:23 +0100
committerYann Herklotz <git@ymhg.org>2019-04-17 19:20:23 +0100
commit43ae318ed36dcf4098a8740029bf6b4bf92e4960 (patch)
treebc5e8cd99d354964b00168fe99a4f24f5a330708 /src/VeriFuzz/Verilog/Gen.hs
parent09792210537446b3400c61c699da8351cfe725dc (diff)
downloadverismith-43ae318ed36dcf4098a8740029bf6b4bf92e4960.tar.gz
verismith-43ae318ed36dcf4098a8740029bf6b4bf92e4960.zip
Reduce the wire size as Quartus was crashing
Diffstat (limited to 'src/VeriFuzz/Verilog/Gen.hs')
-rw-r--r--src/VeriFuzz/Verilog/Gen.hs10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs
index 46cdc25..8ff63ef 100644
--- a/src/VeriFuzz/Verilog/Gen.hs
+++ b/src/VeriFuzz/Verilog/Gen.hs
@@ -16,6 +16,8 @@ module VeriFuzz.Verilog.Gen
( -- * Generation methods
procedural
, proceduralIO
+ , proceduralSrc
+ , proceduralSrcIO
, randomMod
)
where
@@ -104,7 +106,7 @@ largeNum :: Gen Int
largeNum = Hog.int Hog.linearBounded
wireSize :: Gen Int
-wireSize = Hog.int $ Hog.linear 2 200
+wireSize = Hog.int $ Hog.linear 2 100
range :: Gen Range
range = Range <$> fmap fromIntegral wireSize <*> pure 0
@@ -450,3 +452,9 @@ procedural top config = do
proceduralIO :: T.Text -> Config -> IO Verilog
proceduralIO t = Hog.sample . procedural t
+
+proceduralSrc :: T.Text -> Config -> Gen SourceInfo
+proceduralSrc t c = SourceInfo t <$> procedural t c
+
+proceduralSrcIO :: T.Text -> Config -> IO SourceInfo
+proceduralSrcIO t c = SourceInfo t <$> proceduralIO t c