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| author | Yann Herklotz <git@ymhg.org> | 2019-04-23 10:11:27 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-23 10:11:27 +0100 |
| commit | 931b1a60643f50768eb33903e87a7471898835db (patch) | |
| tree | 1e9bc6058324aa90fea37cfad230a3b953349ba1 /src/VeriFuzz/Verilog/Gen.hs | |
| parent | 879d1d3522d5693d8621164cfb09fb830ea2ef0c (diff) | |
| download | verismith-931b1a60643f50768eb33903e87a7471898835db.tar.gz verismith-931b1a60643f50768eb33903e87a7471898835db.zip | |
Add event list generation for always blocks
Diffstat (limited to 'src/VeriFuzz/Verilog/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Gen.hs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Gen.hs b/src/VeriFuzz/Verilog/Gen.hs index 6159766..bf9f84d 100644 --- a/src/VeriFuzz/Verilog/Gen.hs +++ b/src/VeriFuzz/Verilog/Gen.hs @@ -347,8 +347,9 @@ eventList = do always :: StateGen ModItem always = do + events <- eventList stat <- SeqBlock <$> some statement - return $ Always (EventCtrl (EPosEdge "clk") (Just stat)) + return $ Always (EventCtrl events (Just stat)) instantiate :: ModDecl -> StateGen ModItem instantiate (ModDecl i outP inP _ _) = do |