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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 17:20:42 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 17:20:42 +0000 |
| commit | fa4d1bf03003944e8a73ac4e341633020edca6af (patch) | |
| tree | aa2afd8d9fd41430cc1817c45ec618564218056c /src/VeriFuzz/Verilog/Helpers.hs | |
| parent | e0fecd298f622e8943d6ae2bfc7de00fe36e57a7 (diff) | |
| download | verismith-fa4d1bf03003944e8a73ac4e341633020edca6af.tar.gz verismith-fa4d1bf03003944e8a73ac4e341633020edca6af.zip | |
Fix warnings
Diffstat (limited to 'src/VeriFuzz/Verilog/Helpers.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Helpers.hs | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/VeriFuzz/Verilog/Helpers.hs b/src/VeriFuzz/Verilog/Helpers.hs index 0204379..90a5de4 100644 --- a/src/VeriFuzz/Verilog/Helpers.hs +++ b/src/VeriFuzz/Verilog/Helpers.hs @@ -23,9 +23,6 @@ regDecl = Decl Nothing . Port (Reg False) 1 wireDecl :: Identifier -> ModItem wireDecl = Decl Nothing . Port Wire 1 -modConn :: Identifier -> ModConn -modConn = ModConn . Id - -- | Create an empty module. emptyMod :: ModDecl emptyMod = ModDecl "" [] [] [] @@ -48,9 +45,9 @@ testBench = , regDecl "b" , wireDecl "c" , ModInst "and" "and_gate" - [ modConn "c" - , modConn "a" - , modConn "b" + [ ModConn $ Id "c" + , ModConn $ Id "a" + , ModConn $ Id "b" ] , Initial $ SeqBlock [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 |