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| author | Yann Herklotz <git@ymhg.org> | 2019-04-03 17:38:11 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-03 17:38:11 +0100 |
| commit | 29804187ac1aeb6d53985e11e9591dc52633bac0 (patch) | |
| tree | 3aae6fb7cb96f75958d3c07bfc791c8a00fbedb9 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 77559b722fca9c873e29d5735b309c0a8d8f2022 (diff) | |
| download | verismith-29804187ac1aeb6d53985e11e9591dc52633bac0.tar.gz verismith-29804187ac1aeb6d53985e11e9591dc52633bac0.zip | |
Export Vivado types and fix test failure
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index c72463f..69b6d57 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -105,7 +105,7 @@ allVars m = <> (m ^.. modInPorts . traverse . portName) -- $setup --- >>> import VeriFuzz.CodeGen +-- >>> import VeriFuzz.Verilog.CodeGen -- >>> let m = (ModDecl (Identifier "m") [Port Wire False 5 (Identifier "y")] [Port Wire False 5 "x"] []) -- >>> let main = (ModDecl "main" [] [] []) |