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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:52:20 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:52:27 +0100 |
| commit | 720fa7a822a077458cf0b29e9dcdc754a881e8bd (patch) | |
| tree | fa00db795c17bba78b02de2823c1092fae1d81ec /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | f3268d934a9a2b01633b5f7a3353d1a97c40a9df (diff) | |
| download | verismith-720fa7a822a077458cf0b29e9dcdc754a881e8bd.tar.gz verismith-720fa7a822a077458cf0b29e9dcdc754a881e8bd.zip | |
Format all files
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 7496935..0fb4c49 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -377,7 +377,14 @@ removeId i = transform trans combineAssigns :: Port -> [ModItem] -> [ModItem] combineAssigns p a = - a <> [ModCA . ContAssign (p ^. portName) . UnOp UnXor . fold $ Id <$> assigns] + a + <> [ ModCA + . ContAssign (p ^. portName) + . UnOp UnXor + . fold + $ Id + <$> assigns + ] where assigns = a ^.. traverse . modContAssign . contAssignNetLVal combineAssigns_ :: Bool -> Port -> [Port] -> ModItem |