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| author | Yann Herklotz <git@ymhg.org> | 2019-05-11 22:14:42 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-11 22:14:42 +0100 |
| commit | 9637980a562d79582689daa5dff43814a531f900 (patch) | |
| tree | 311fba411d26af930b1662f42c9648a48326c2d5 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 6218c8fd0f7dae36bda08fd2b132901e4707584a (diff) | |
| download | verismith-9637980a562d79582689daa5dff43814a531f900.tar.gz verismith-9637980a562d79582689daa5dff43814a531f900.zip | |
Implement module item reduction properly
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index 3f0ae83..66f3c37 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -49,6 +49,7 @@ import VeriFuzz.Circuit.Internal import VeriFuzz.Internal import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.BitVec +import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Internal class Mutate a where @@ -146,6 +147,9 @@ instance Mutate a => Mutate [a] where instance Mutate a => Mutate (Maybe a) where mutExpr f a = mutExpr f <$> a +instance Mutate a => Mutate (GenVerilog a) where + mutExpr f (GenVerilog a) = GenVerilog $ mutExpr f a + -- | Return if the 'Identifier' is in a 'ModDecl'. inPort :: Identifier -> ModDecl -> Bool inPort i m = inInput |