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| author | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:48 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:48 +0100 |
| commit | 4b5401ef3400413be0559dfa17718611822fc4c6 (patch) | |
| tree | f57cd74848f1f07454724e1d49369e6847f50ae7 /src/VeriFuzz/Verilog/Mutate.hs | |
| parent | 310171c8891b61958c10a701f4837db3238582a8 (diff) | |
| download | verismith-4b5401ef3400413be0559dfa17718611822fc4c6.tar.gz verismith-4b5401ef3400413be0559dfa17718611822fc4c6.zip | |
Generate flip-flops instead of latches
Diffstat (limited to 'src/VeriFuzz/Verilog/Mutate.hs')
| -rw-r--r-- | src/VeriFuzz/Verilog/Mutate.hs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/VeriFuzz/Verilog/Mutate.hs b/src/VeriFuzz/Verilog/Mutate.hs index eca472f..03ee1d0 100644 --- a/src/VeriFuzz/Verilog/Mutate.hs +++ b/src/VeriFuzz/Verilog/Mutate.hs @@ -206,13 +206,12 @@ makeTop i m = ModDecl (m ^. modId) ys (m ^. modInPorts) modIt -- | Make a top module with an assert that requires @y_1@ to always be equal to -- @y_2@, which can then be proven using a formal verification tool. makeTopAssert :: ModDecl -> ModDecl -makeTopAssert = (modItems %~ (++ [assert])) . (modInPorts %~ addClk) . makeTop +makeTopAssert = (modItems %~ (++ [assert])) . makeTop 2 where assert = Always . EventCtrl e . Just $ SeqBlock [TaskEnable $ Task "assert" [BinOp (Id "y_1") BinEq (Id "y_2")]] e = EPosEdge "clk" - addClk = (defaultPort "clk" :) -- | Provide declarations for all the ports that are passed to it. declareMod :: [Port] -> ModDecl -> ModDecl |