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| author | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
| commit | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch) | |
| tree | 042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz/Yosys.hs | |
| parent | 1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff) | |
| download | verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip | |
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Yosys.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index b6da8c2..ef2bc11 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -37,7 +37,7 @@ defaultYosys = Yosys "yosys" writeSimFile :: Yosys -- ^ Simulator instance - -> VerilogSrc -- ^ Current Verilog source + -> Verilog -- ^ Current Verilog source -> FilePath -- ^ Output sim file -> Sh () writeSimFile _ src file = do |