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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-03 01:31:04 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-03 01:31:04 +0000 |
| commit | 58590e754c90d46b6ef0c5746d0b7e70a0aa13b4 (patch) | |
| tree | 54588e468d807b20d87b6b229a9a574b451053ab /src/VeriFuzz/Yosys.hs | |
| parent | ad5d8bced5aec1e887c44e7e3c26a9b74c5a3ba5 (diff) | |
| download | verismith-58590e754c90d46b6ef0c5746d0b7e70a0aa13b4.tar.gz verismith-58590e754c90d46b6ef0c5746d0b7e70a0aa13b4.zip | |
Fix logging
Diffstat (limited to 'src/VeriFuzz/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Yosys.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index d7b0014..b11003e 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -48,7 +48,7 @@ runSynthYosys sim m outf = do dir <- pwd writefile inpf $ genSource m echoP "Yosys: synthesis" - _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] + _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-b", "verilog -noattr", "-o", out, "-S", inp] echoP "Yosys: synthesis done" where inpf = "rtl.v" |