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| author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-03-01 19:18:05 +0000 |
|---|---|---|
| committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-03-01 19:18:05 +0000 |
| commit | ad199f8087642573f4f7daeeb588a43faaa3eab3 (patch) | |
| tree | 067e3ee13861e2ed8141e196a9fe9d96b3191b0b /src/VeriFuzz/Yosys.hs | |
| parent | dba53cd980a215936cffaedb84ad1e4c0784beee (diff) | |
| download | verismith-ad199f8087642573f4f7daeeb588a43faaa3eab3.tar.gz verismith-ad199f8087642573f4f7daeeb588a43faaa3eab3.zip | |
Add lens to access main module in SourceInfo
Diffstat (limited to 'src/VeriFuzz/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Yosys.hs | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index d33e399..9f605db 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -14,6 +14,7 @@ Yosys simulator implementation. module VeriFuzz.Yosys where +import Control.Lens import Prelude hiding (FilePath) import Shelly import Text.Shakespeare.Text (st) @@ -72,7 +73,7 @@ runEquivYosys -> SourceInfo -> Sh () runEquivYosys yosys sim1 sim2 srcInfo = do - writefile "top.v" . genSource . initMod . makeTop 2 $ mainModule srcInfo + writefile "top.v" . genSource . initMod . makeTop 2 $ srcInfo ^. mainModule writefile checkFile $ yosysSatConfig sim1 sim2 srcInfo runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|] runMaybeSynth sim2 srcInfo @@ -94,7 +95,12 @@ runEquiv _ sim1 sim2 srcInfo = do root <- rootPath dir <- pwd echoP "SymbiYosys: setup" - writefile "top.v" . genSource . initMod . makeTopAssert $ mainModule srcInfo + writefile "top.v" + . genSource + . initMod + . makeTopAssert + $ srcInfo + ^. mainModule writefile "test.sby" $ sbyConfig root sim1 sim2 srcInfo runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|] runMaybeSynth sim2 srcInfo |