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author | Yann Herklotz <git@yannherklotz.com> | 2020-05-12 12:21:36 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-05-12 12:21:42 +0100 |
commit | 7124a4f00e536b4d5323a7488c1f65469dddb102 (patch) | |
tree | 150ccfd9bf1549c930a12ee5200826cedfa37fa3 /src/Verismith/Circuit.hs | |
parent | d1b04fc068b1484f8bd0020598d3a2f023772f46 (diff) | |
download | verismith-7124a4f00e536b4d5323a7488c1f65469dddb102.tar.gz verismith-7124a4f00e536b4d5323a7488c1f65469dddb102.zip |
Format with ormolu
Diffstat (limited to 'src/Verismith/Circuit.hs')
-rw-r--r-- | src/Verismith/Circuit.hs | 76 |
1 files changed, 37 insertions, 39 deletions
diff --git a/src/Verismith/Circuit.hs b/src/Verismith/Circuit.hs index cda2f4f..c91991d 100644 --- a/src/Verismith/Circuit.hs +++ b/src/Verismith/Circuit.hs @@ -1,45 +1,43 @@ -{-| -Module : Verismith.Circuit -Description : Definition of the circuit graph. -Copyright : (c) 2018-2019, Yann Herklotz -License : GPL-3 -Maintainer : yann [at] yannherklotz [dot] com -Stability : experimental -Portability : POSIX - -Definition of the circuit graph. --} - +-- | +-- Module : Verismith.Circuit +-- Description : Definition of the circuit graph. +-- Copyright : (c) 2018-2019, Yann Herklotz +-- License : GPL-3 +-- Maintainer : yann [at] yannherklotz [dot] com +-- Stability : experimental +-- Portability : POSIX +-- +-- Definition of the circuit graph. module Verismith.Circuit - ( -- * Circuit - Gate(..) - , Circuit(..) - , CNode(..) - , CEdge(..) - , fromGraph - , generateAST - , rDups - , rDupsCirc - , randomDAG - , genRandomDAG - ) + ( -- * Circuit + Gate (..), + Circuit (..), + CNode (..), + CEdge (..), + fromGraph, + generateAST, + rDups, + rDupsCirc, + randomDAG, + genRandomDAG, + ) where -import Control.Lens -import Hedgehog (Gen) -import qualified Hedgehog.Gen as Hog -import Verismith.Circuit.Base -import Verismith.Circuit.Gen -import Verismith.Circuit.Random -import Verismith.Verilog.AST -import Verismith.Verilog.Mutate +import Control.Lens +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import Verismith.Circuit.Base +import Verismith.Circuit.Gen +import Verismith.Circuit.Random +import Verismith.Verilog.AST +import Verismith.Verilog.Mutate fromGraph :: Gen (ModDecl ann) fromGraph = do - gr <- rDupsCirc <$> Hog.resize 100 randomDAG - return - $ initMod - . head - $ nestUpTo 5 (generateAST gr) - ^.. _Wrapped - . traverse + gr <- rDupsCirc <$> Hog.resize 100 randomDAG + return + $ initMod + . head + $ nestUpTo 5 (generateAST gr) + ^.. _Wrapped + . traverse |