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author | Yann Herklotz <git@yannherklotz.com> | 2020-03-16 13:12:30 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-03-16 13:12:30 +0000 |
commit | 472aedf5daeb1cb0d095a63eacf259b798f56586 (patch) | |
tree | 8e7e32b3ff2d762b90d8b460926adb83408a6263 /src/Verismith/Circuit | |
parent | 010d7343133ebe53a472b9d26fdeb509db31d4c9 (diff) | |
download | verismith-472aedf5daeb1cb0d095a63eacf259b798f56586.tar.gz verismith-472aedf5daeb1cb0d095a63eacf259b798f56586.zip |
WIP changes to the AST types
Diffstat (limited to 'src/Verismith/Circuit')
-rw-r--r-- | src/Verismith/Circuit/Gen.hs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/Verismith/Circuit/Gen.hs b/src/Verismith/Circuit/Gen.hs index c5cb697..07b6c06 100644 --- a/src/Verismith/Circuit/Gen.hs +++ b/src/Verismith/Circuit/Gen.hs @@ -53,20 +53,20 @@ genAssignExpr g (n : ns) = BinOp wire oper <$> genAssignExpr g ns -- | Generate the continuous assignment AST for a particular node. If it does -- not have any nodes that link to it then return 'Nothing', as that means that -- the assignment will just be empty. -genContAssignAST :: Circuit -> LNode Gate -> Maybe ModItem +genContAssignAST :: Circuit -> LNode Gate -> Maybe (ModItem ann) genContAssignAST c (n, g) = ModCA . ContAssign name <$> genAssignExpr g nodes where gr = getCircuit c nodes = G.pre gr n name = frNode n -genAssignAST :: Circuit -> [ModItem] +genAssignAST :: Circuit -> [ModItem ann] genAssignAST c = catMaybes $ genContAssignAST c <$> nodes where gr = getCircuit c nodes = G.labNodes gr -genModuleDeclAST :: Circuit -> ModDecl +genModuleDeclAST :: Circuit -> (ModDecl ann) genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) [] where i = Identifier "gen_module" @@ -75,5 +75,5 @@ genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) [] a = genAssignAST c yPort = Port Wire False 90 "y" -generateAST :: Circuit -> Verilog +generateAST :: Circuit -> (Verilog ann) generateAST c = Verilog [genModuleDeclAST c] |