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| author | Yann Herklotz <git@yannherklotz.com> | 2019-12-03 20:03:17 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-12-03 20:03:17 +0000 |
| commit | d29813263852c866f20f88504860120820499411 (patch) | |
| tree | 7f224cbfba855f3cd9c94911fcd863824de251fd /src/Verismith/Tool/Template.hs | |
| parent | c59a9178c701f4a514b980d0b8d66a6bd238fb19 (diff) | |
| download | verismith-d29813263852c866f20f88504860120820499411.tar.gz verismith-d29813263852c866f20f88504860120820499411.zip | |
Do not run counter example if no rerunner is specified
Diffstat (limited to 'src/Verismith/Tool/Template.hs')
| -rw-r--r-- | src/Verismith/Tool/Template.hs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index 0b63e91..ffa7240 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -26,6 +26,7 @@ module Verismith.Tool.Template where import Control.Lens ((^..)) +import Data.Maybe (fromMaybe) import Data.Text (Text) import qualified Data.Text as T import Prelude hiding (FilePath) @@ -136,11 +137,11 @@ synth_design -part xc7k70t -top #{top} write_verilog -force #{outf} |] -sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> b -> SourceInfo -> Text -sbyConfig datadir sim1 sim2 (SourceInfo top _) = [st|[options] +sbyConfig :: (Synthesiser a, Synthesiser b) => Maybe Text -> FilePath -> a -> b -> SourceInfo -> Text +sbyConfig mt datadir sim1 sim2 (SourceInfo top _) = [st|[options] multiclock on mode prove -aigsmt none +aigsmt #{fromMaybe "none" mt} [engines] abc pdr |