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author | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 19:48:38 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-11-14 19:48:38 +0000 |
commit | d821bbe66596b402a93c3189d5497e4d287f6a83 (patch) | |
tree | 382294b18359953bef5e9205690f1000c08b7bd8 /src/Verismith/Tool/Template.hs | |
parent | 7a9d412a378a8bbf2f68b44504a1df148c2837cc (diff) | |
download | verismith-d821bbe66596b402a93c3189d5497e4d287f6a83.tar.gz verismith-d821bbe66596b402a93c3189d5497e4d287f6a83.zip |
Support proper Quartus Pro version
Diffstat (limited to 'src/Verismith/Tool/Template.hs')
-rw-r--r-- | src/Verismith/Tool/Template.hs | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index 5402702..3bd5a2d 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -16,6 +16,7 @@ module Verismith.Tool.Template ( yosysSynthConfigStd , yosysSatConfig , yosysSimConfig + , quartusLightSynthConfig , quartusSynthConfig , xstSynthConfig , vivadoSynthConfig @@ -77,10 +78,10 @@ yosysSimConfig = [st|read_verilog rtl.v; proc;; rename mod mod_rtl |] -quartusSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text -quartusSynthConfig q sdc top fp = [st|load_package flow +quartusLightSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text +quartusLightSynthConfig q sdc top fp = [st|load_package flow -project_new #{top} +project_new -overwrite #{top} set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name SYSTEMVERILOG_FILE #{toTextIgnore fp} @@ -98,6 +99,25 @@ execute_module -tool eda -args "--simulation --tool=vcs" project_close |] +quartusSynthConfig :: Synthesiser a => a -> FilePath -> Text -> FilePath -> Text +quartusSynthConfig q sdc top fp = [st|load_package flow + +project_new -overwrite #{top} + +set_global_assignment -name FAMILY "Cyclone 10 GX" +set_global_assignment -name SYSTEMVERILOG_FILE #{toTextIgnore fp} +set_global_assignment -name TOP_LEVEL_ENTITY #{top} +set_global_assignment -name SDC_FILE #{toTextIgnore sdc} +set_global_assignment -name INI_VARS "qatm_force_vqm=on;" +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 +set_instance_assignment -name VIRTUAL_PIN ON -to * + +execute_module -tool syn +execute_module -tool eda -args "--simulation --tool=vcs" + +project_close +|] + xstSynthConfig :: Text -> Text xstSynthConfig top = [st|run -ifn #{top}.prj -ofn #{top} -p artix7 -top #{top} |