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| author | Yann Herklotz <git@yannherklotz.com> | 2020-04-06 23:03:46 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-04-06 23:03:46 +0100 |
| commit | 2b00c249a29236af734c1e5b717b859a2a54a5dc (patch) | |
| tree | 070cf697a962f3b09e673b2fee9be541e3e90788 /src/Verismith/Verilog/AST.hs | |
| parent | d31472164e711a330e9f0a5b0a486b12abb69daf (diff) | |
| parent | 472aedf5daeb1cb0d095a63eacf259b798f56586 (diff) | |
| download | verismith-2b00c249a29236af734c1e5b717b859a2a54a5dc.tar.gz verismith-2b00c249a29236af734c1e5b717b859a2a54a5dc.zip | |
Merge branch 'develop' of github.com:ymherklotz/verismith into develop
Diffstat (limited to 'src/Verismith/Verilog/AST.hs')
| -rw-r--r-- | src/Verismith/Verilog/AST.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Verismith/Verilog/AST.hs b/src/Verismith/Verilog/AST.hs index 9a71022..74c3cfb 100644 --- a/src/Verismith/Verilog/AST.hs +++ b/src/Verismith/Verilog/AST.hs @@ -364,7 +364,7 @@ instance Num Range where -- cumbersome than useful, as a lot of ports can be declared without input and -- output port. -- --- This is now implemented inside 'ModDecl' itself, which uses a list of output +-- This is now implemented inside '(ModDecl ann)' itself, which uses a list of output -- and input ports. data Port = Port { _portType :: !PortType @@ -547,7 +547,7 @@ traverseModConn :: (Applicative f) => (Expr -> f Expr) -> ModConn -> f ModConn traverseModConn f (ModConn e ) = ModConn <$> f e traverseModConn f (ModConnNamed a e) = ModConnNamed a <$> f e -traverseModItem :: (Applicative f) => (Expr -> f Expr) -> ModItem a -> f (ModItem a) +traverseModItem :: (Applicative f) => (Expr -> f Expr) -> (ModItem ann) -> f (ModItem ann) traverseModItem f (ModCA (ContAssign a e)) = ModCA . ContAssign a <$> f e traverseModItem f (ModInst a b e) = ModInst a b <$> sequenceA (traverseModConn f <$> e) |