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author | Yann Herklotz <git@yannherklotz.com> | 2021-04-26 11:38:55 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-04-26 11:38:55 +0100 |
commit | 326048aeac6f846d8ad52c2a66f73219426f8bea (patch) | |
tree | a86c5a045e47900d9d78be680cf3e43a0454131b /src/Verismith/Verilog/AST.hs | |
parent | 773acb06f15d49b810b76508505f5df5a84f8172 (diff) | |
download | verismith-326048aeac6f846d8ad52c2a66f73219426f8bea.tar.gz verismith-326048aeac6f846d8ad52c2a66f73219426f8bea.zip |
Fix parser for a larger set of inputs
- Added support for parameter parsing
- Added support for parameter declaration for instantiations
- Fix parsing of @(*)
- Fix parsing of `timescale
- Add parsing for case statements with default
Diffstat (limited to 'src/Verismith/Verilog/AST.hs')
-rw-r--r-- | src/Verismith/Verilog/AST.hs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/Verismith/Verilog/AST.hs b/src/Verismith/Verilog/AST.hs index ca0d380..b30688d 100644 --- a/src/Verismith/Verilog/AST.hs +++ b/src/Verismith/Verilog/AST.hs @@ -663,6 +663,7 @@ data ModItem a = ModCA {_modContAssign :: !ContAssign} | ModInst { _modInstId :: {-# UNPACK #-} !Identifier, + _modInstDecl :: [ModConn], _modInstName :: {-# UNPACK #-} !Identifier, _modInstConns :: [ModConn] } @@ -687,7 +688,7 @@ instance Functor ModItem where fmap f (Initial s) = Initial $ fmap f s fmap f (Always s) = Always $ fmap f s fmap _ (ModCA c) = ModCA c - fmap _ (ModInst a b c) = ModInst a b c + fmap _ (ModInst a b c d) = ModInst a b c d fmap _ (Decl a b c) = Decl a b c fmap _ (ParamDecl p) = ParamDecl p fmap _ (LocalParamDecl l) = LocalParamDecl l @@ -726,8 +727,8 @@ traverseModConn f (ModConnNamed a e) = ModConnNamed a <$> f e traverseModItem :: (Applicative f) => (Expr -> f Expr) -> (ModItem ann) -> f (ModItem ann) traverseModItem f (ModCA (ContAssign a e)) = ModCA . ContAssign a <$> f e -traverseModItem f (ModInst a b e) = - ModInst a b <$> sequenceA (traverseModConn f <$> e) +traverseModItem f (ModInst a b c e) = + ModInst a b c <$> sequenceA (traverseModConn f <$> e) traverseModItem _ e = pure e -- | The complete sourcetext for the Verilog module. |