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authorYann Herklotz <git@yannherklotz.com>2020-01-06 21:09:09 +0000
committerYann Herklotz <git@yannherklotz.com>2020-01-06 21:09:09 +0000
commit9b28c903dc430d0e48b62091053c4c06829e75c7 (patch)
tree33ddef073993ac4a2ce898438874638683e92ec2 /src/Verismith/Verilog/Preprocess.hs
parentcdf2521e4a1a8f640187cbcc4fd01b64beed175a (diff)
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Diffstat (limited to 'src/Verismith/Verilog/Preprocess.hs')
-rw-r--r--src/Verismith/Verilog/Preprocess.hs2
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diff --git a/src/Verismith/Verilog/Preprocess.hs b/src/Verismith/Verilog/Preprocess.hs
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--- a/src/Verismith/Verilog/Preprocess.hs
+++ b/src/Verismith/Verilog/Preprocess.hs
@@ -2,7 +2,7 @@
Module : Verismith.Verilog.Preprocess
Description : Simple preprocessor for `define and comments.
Copyright : (c) 2011-2015 Tom Hawkins, 2019 Yann Herklotz
-License : GPLv3
+License : GPL-3
Maintainer : yann [at] yannherklotz [dot] com
Stability : experimental
Portability : POSIX