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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-08 15:49:36 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-08 15:49:36 +0000 |
| commit | 7239f17dafcd5eb2c742cdd20e88a7256d977108 (patch) | |
| tree | b2e8e19a382dbdc018e5e0fd5ce0d2d41801f83a /src | |
| parent | 63c737f30b22595bf4eaccde5c7f6cdc67206132 (diff) | |
| download | verismith-7239f17dafcd5eb2c742cdd20e88a7256d977108.tar.gz verismith-7239f17dafcd5eb2c742cdd20e88a7256d977108.zip | |
Remove _ModCA and replace it by modContAssign
Diffstat (limited to 'src')
| -rw-r--r-- | src/VeriFuzz/ASTGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs index 5d4d8bc..d113bbb 100644 --- a/src/VeriFuzz/ASTGen.hs +++ b/src/VeriFuzz/ASTGen.hs @@ -75,7 +75,7 @@ genModuleDeclAST c = ModDecl i output ports items output = [Port Wire 90 "y"] a = genAssignAST c items = a ++ [ModCA . ContAssign "y" . fold $ Id <$> assigns] - assigns = a ^.. traverse . _ModCA . contAssignNetLVal + assigns = a ^.. traverse . modContAssign . contAssignNetLVal generateAST :: Circuit -> VerilogSrc generateAST c = VerilogSrc [Description $ genModuleDeclAST c] |