Add Verilog AST

1 files changed, 13 insertions, 0 deletions

diff --git a/src/Test/VeriFuzz/VerilogAST.hs b/src/Test/VeriFuzz/VerilogAST.hs
new file mode 100644
index 0000000..897855b
--- /dev/null
+++ b/src/Test/VeriFuzz/VerilogAST.hs
@@ -0,0 +1,13 @@
+module Test.VeriFuzz.VerilogAST where
+
+data ModuleItem = 
+
+-- | 'module' module_identifier [list_of_ports] ';' { module_item } 'end_module'
+data ModuleDecl = ModuleDecl { moduleId   :: Text
+                             , ports      :: [Port]
+                             , moduleItem :: ModuleItem
+                             }
+
+type Description = ModuleDecl
+
+type SourceText = [Description]