Move helper functions

3 files changed, 7 insertions, 5 deletions

diff --git a/src/Test/VeriFuzz.hs b/src/Test/VeriFuzz.hs
index a16b095..a3204b3 100644
--- a/src/Test/VeriFuzz.hs
+++ b/src/Test/VeriFuzz.hs
@@ -14,8 +14,6 @@ module Test.VeriFuzz
     module Test.VeriFuzz.Circuit
     -- * Verilog AST Data Types
   , module Test.VeriFuzz.Verilog
-    -- * Helpers
-  , module Test.VeriFuzz.Helpers
     -- * Graphs
   , module Test.VeriFuzz.Graph.ASTGen
   , module Test.VeriFuzz.Graph.CodeGen
@@ -28,6 +26,5 @@ import           Test.VeriFuzz.Circuit
 import           Test.VeriFuzz.Graph.ASTGen
 import           Test.VeriFuzz.Graph.CodeGen
 import           Test.VeriFuzz.Graph.Random
-import           Test.VeriFuzz.Helpers
 import           Test.VeriFuzz.Simulator
 import           Test.VeriFuzz.Verilog
diff --git a/src/Test/VeriFuzz/Verilog.hs b/src/Test/VeriFuzz/Verilog.hs
index 3fa4747..072dc75 100644
--- a/src/Test/VeriFuzz/Verilog.hs
+++ b/src/Test/VeriFuzz/Verilog.hs
@@ -17,8 +17,10 @@ module Test.VeriFuzz.Verilog
   , module Test.VeriFuzz.Verilog.CodeGen
     -- * Verilog mutations
   , module Test.VeriFuzz.Verilog.Mutate
+  , module Test.VeriFuzz.Verilog.Helpers
   ) where
 
 import           Test.VeriFuzz.Verilog.AST
 import           Test.VeriFuzz.Verilog.CodeGen
+import           Test.VeriFuzz.Verilog.Helpers
 import           Test.VeriFuzz.Verilog.Mutate
diff --git a/src/Test/VeriFuzz/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index 6643683..d4a7c9c 100644
--- a/src/Test/VeriFuzz/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -1,5 +1,5 @@
 {-|
-Module      : Test.VeriFuzz.Default
+Module      : Test.VeriFuzz.VeriFuzz.Helpers
 Description : Defaults and common functions.
 Copyright   : (c) 2018-2019, Yann Herklotz Grave
 License     : BSD-3
@@ -10,7 +10,7 @@ Portability : POSIX
 Defaults and common functions.
 -}
 
-module Test.VeriFuzz.Helpers where
+module Test.VeriFuzz.VeriFuzz.Helpers where
 
 import           Control.Lens
 import           Data.Text                 (Text)
@@ -71,3 +71,6 @@ testBench =
 
 addTestBench :: VerilogSrc -> VerilogSrc
 addTestBench = addDescription $ Description testBench
+
+defaultPort :: Identifier -> Port
+defaultPort = Port (PortNet Wire) 1