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authorYann Herklotz <git@ymhg.org>2019-04-14 20:21:15 +0100
committerYann Herklotz <git@ymhg.org>2019-04-14 20:21:15 +0100
commiteae8ed5fd46ff2d78bdf28cd437be57654f638c5 (patch)
tree7c7b329fd357c27a784ad34ded274c836e5389f0 /stack.yaml
parent73b7b059a463e40f7a223d179ba42d17696a4a33 (diff)
downloadverismith-eae8ed5fd46ff2d78bdf28cd437be57654f638c5.tar.gz
verismith-eae8ed5fd46ff2d78bdf28cd437be57654f638c5.zip
Add BitVec type to model Verilog bit vectors
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