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| author | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:21:18 +0100 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2018-12-28 19:21:18 +0100 |
| commit | 3b5b7e33033799ab1eb2289615a2c96b6329cba4 (patch) | |
| tree | 08d43b024daf99cfc8ec8f82bc223a9a04f83681 /tests/Unit.hs | |
| parent | 5243210a4c16a7349b59a964072c4effb3aea30a (diff) | |
| download | verismith-3b5b7e33033799ab1eb2289615a2c96b6329cba4.tar.gz verismith-3b5b7e33033799ab1eb2289615a2c96b6329cba4.zip | |
Fix imports and cabal file
Diffstat (limited to 'tests/Unit.hs')
| -rw-r--r-- | tests/Unit.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/Unit.hs b/tests/Unit.hs index 440953a..67f642c 100644 --- a/tests/Unit.hs +++ b/tests/Unit.hs @@ -43,7 +43,7 @@ runMain = do gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) -- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png", -- T.putStrLn $ generate gr - --g <- QC.generate (QC.arbitrary :: QC.Gen SourceText) + --g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc) let x = generateAST $ Circuit gr - let y = head . reverse $ x ^.. getSourceText . traverse . getDescription . moduleItems . traverse . _ModCA . contAssignExpr + let y = head . reverse $ x ^.. getVerilogSrc . traverse . getDescription . moduleItems . traverse . _ModCA . contAssignExpr print $ transformOf traverseExpr trans y |