diff options
| -rw-r--r-- | src/VeriFuzz/General.hs | 3 | ||||
| -rw-r--r-- | src/VeriFuzz/Yosys.hs | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/VeriFuzz/General.hs b/src/VeriFuzz/General.hs index 37a8f90..9b8f5c5 100644 --- a/src/VeriFuzz/General.hs +++ b/src/VeriFuzz/General.hs @@ -73,4 +73,5 @@ logger :: FilePath -> Text -> Sh a -> Sh a logger fp name = log_stderr_with (l "_log.stderr.txt") . log_stdout_with (l "_log.txt") where - l s = writeFile (T.unpack (toTextIgnore $ fp </> fromText name) <> s) . T.unpack + l s t = appendFile (file s) (T.unpack t) >> appendFile (file s) "\n" + file s = T.unpack (toTextIgnore $ fp </> fromText name) <> s diff --git a/src/VeriFuzz/Yosys.hs b/src/VeriFuzz/Yosys.hs index d7b0014..b11003e 100644 --- a/src/VeriFuzz/Yosys.hs +++ b/src/VeriFuzz/Yosys.hs @@ -48,7 +48,7 @@ runSynthYosys sim m outf = do dir <- pwd writefile inpf $ genSource m echoP "Yosys: synthesis" - _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-q", "-b", "verilog -noattr", "-o", out, "-S", inp] + _ <- logger dir "yosys" $ timeout (yosysPath sim) ["-b", "verilog -noattr", "-o", out, "-S", inp] echoP "Yosys: synthesis done" where inpf = "rtl.v" |