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-rw-r--r--src/Test/VeriFuzz/Simulator.hs23
-rw-r--r--src/Test/VeriFuzz/Simulator/General.hs48
-rw-r--r--src/Test/VeriFuzz/Simulator/Icarus.hs35
-rw-r--r--src/Test/VeriFuzz/Simulator/Xst.hs52
-rw-r--r--src/Test/VeriFuzz/Simulator/Yosys.hs57
5 files changed, 215 insertions, 0 deletions
diff --git a/src/Test/VeriFuzz/Simulator.hs b/src/Test/VeriFuzz/Simulator.hs
new file mode 100644
index 0000000..6eb01ad
--- /dev/null
+++ b/src/Test/VeriFuzz/Simulator.hs
@@ -0,0 +1,23 @@
+{-|
+Module : Test.VeriFuzz.Simulator
+Description : Simulator module.
+Copyright : (c) Yann Herklotz Grave 2018
+License : GPL-3
+Maintainer : ymherklotz@gmail.com
+Stability : experimental
+Portability : POSIX
+
+Simulator module.
+-}
+
+module Test.VeriFuzz.Simulator
+ ( module Test.VeriFuzz.Simulator.General
+ , module Test.VeriFuzz.Simulator.Yosys
+ , module Test.VeriFuzz.Simulator.Xst
+ , module Test.VeriFuzz.Simulator.Icarus
+ ) where
+
+import Test.VeriFuzz.Simulator.General
+import Test.VeriFuzz.Simulator.Icarus
+import Test.VeriFuzz.Simulator.Xst
+import Test.VeriFuzz.Simulator.Yosys
diff --git a/src/Test/VeriFuzz/Simulator/General.hs b/src/Test/VeriFuzz/Simulator/General.hs
new file mode 100644
index 0000000..e5307ea
--- /dev/null
+++ b/src/Test/VeriFuzz/Simulator/General.hs
@@ -0,0 +1,48 @@
+{-|
+Module : Test.VeriFuzz.Simulator.General
+Description : Class of the simulator.
+Copyright : (c) Yann Herklotz Grave 2018
+License : GPL-3
+Maintainer : ymherklotz@gmail.com
+Stability : experimental
+Portability : POSIX
+
+Class of the simulator and the synthesize tool.
+-}
+
+module Test.VeriFuzz.Simulator.General where
+
+import Data.Text (Text)
+import Prelude hiding (FilePath)
+import Shelly
+import Test.VeriFuzz.Verilog.AST
+
+-- | Simulator class.
+class Simulator a where
+ toText :: a -> Text
+
+-- | Simulation type class.
+class (Simulator a) => Simulate a where
+ runSim :: a -- ^ Simulator instance
+ -> ModDecl -- ^ Module to simulate
+ -> [Int] -- ^ Inputs to simulate
+ -> Sh Int -- ^ Returns the value of the hash at the output of the testbench
+
+-- | Synthesize type class.
+class (Simulator a) => Synthesize a where
+ runSynth :: a -- ^ Synthesize tool instance
+ -> ModDecl -- ^ Module to synthesize
+ -> FilePath -- ^ Output verilog file for the module
+ -> Sh () -- ^ does not return any values
+
+timeout :: Text -> [Text] -> Sh Text
+timeout = command1 "timeout" ["180"]
+
+timeout_ :: Text -> [Text] -> Sh ()
+timeout_ = command1_ "timeout" ["180"]
+
+synthesizers :: [Text]
+synthesizers = ["yosys", "xst"]
+
+simulators :: [Text]
+simulators = ["yosim", "iverilog"]
diff --git a/src/Test/VeriFuzz/Simulator/Icarus.hs b/src/Test/VeriFuzz/Simulator/Icarus.hs
new file mode 100644
index 0000000..10b72e0
--- /dev/null
+++ b/src/Test/VeriFuzz/Simulator/Icarus.hs
@@ -0,0 +1,35 @@
+{-|
+Module : Test.VeriFuzz.Simulator.Icarus
+Description : Icarus verilog module.
+Copyright : (c) Yann Herklotz Grave 2018
+License : GPL-3
+Maintainer : ymherklotz@gmail.com
+Stability : experimental
+Portability : POSIX
+
+Icarus verilog module.
+-}
+
+{-# LANGUAGE QuasiQuotes #-}
+
+module Test.VeriFuzz.Simulator.Icarus where
+
+import Data.Text (Text)
+import qualified Data.Text as T
+import Prelude hiding (FilePath)
+import Shelly
+import Test.VeriFuzz.Simulator.General
+import Test.VeriFuzz.Verilog.AST
+import Test.VeriFuzz.Verilog.CodeGen
+import Text.Shakespeare.Text (st)
+
+data Icarus = Icarus { icarusPath :: FilePath }
+
+instance Simulator Icarus where
+ toText _ = "iverilog"
+
+instance Simulate Icarus where
+ runSim = runSimIcarus
+
+runSimIcarus :: Icarus -> ModDecl -> [Int] -> Sh Int
+runSimIcarus sim mod inp = return 0
diff --git a/src/Test/VeriFuzz/Simulator/Xst.hs b/src/Test/VeriFuzz/Simulator/Xst.hs
new file mode 100644
index 0000000..cfa229d
--- /dev/null
+++ b/src/Test/VeriFuzz/Simulator/Xst.hs
@@ -0,0 +1,52 @@
+{-|
+Module : Test.VeriFuzz.Simulator.Xst
+Description : Xst (ise) simulator implementation.
+Copyright : (c) Yann Herklotz Grave 2018
+License : GPL-3
+Maintainer : ymherklotz@gmail.com
+Stability : experimental
+Portability : POSIX
+
+Xst (ise) simulator implementation.
+-}
+
+{-# LANGUAGE QuasiQuotes #-}
+
+module Test.VeriFuzz.Simulator.Xst where
+
+import Control.Lens hiding ((<.>))
+import Data.Text (Text)
+import qualified Data.Text as T
+import Prelude hiding (FilePath)
+import Shelly
+import Test.VeriFuzz.Simulator.General
+import Test.VeriFuzz.Verilog.AST
+import Test.VeriFuzz.Verilog.CodeGen
+import Text.Shakespeare.Text (st)
+
+data Xst = Xst { xstPath :: FilePath }
+
+instance Simulator Xst where
+ toText _ = "xst"
+
+instance Synthesize Xst where
+ runSynth = runSynthXst
+
+runSynthXst :: Xst -> ModDecl -> FilePath -> Sh ()
+runSynthXst sim mod outf = do
+ writefile xstFile [st|run
+-ifn #{modName}.prj -ofn #{modName} -p artix7 -top #{modName}
+-iobuf NO -ram_extract NO -rom_extract NO -use_dsp48 NO
+-fsm_extract YES -fsm_encoding Auto
+-change_error_to_warning "HDLCompiler:226 HDLCompiler:1832"
+|]
+ writefile prjFile [st|verilog work "#{modName}.v"|]
+ writefile vFile $ genSource mod
+ timeout_ "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" ["-ifn", toTextIgnore xstFile]
+ run_ "netgen" ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", "output.v"]
+ where
+ modName = mod ^. moduleId . getIdentifier
+ modFile = fromText modName
+ xstFile = modFile <.> "xst"
+ prjFile = modFile <.> "prj"
+ vFile = modFile <.> "v"
diff --git a/src/Test/VeriFuzz/Simulator/Yosys.hs b/src/Test/VeriFuzz/Simulator/Yosys.hs
new file mode 100644
index 0000000..33752c4
--- /dev/null
+++ b/src/Test/VeriFuzz/Simulator/Yosys.hs
@@ -0,0 +1,57 @@
+{-|
+Module : Test.VeriFuzz.Simulator.Yosys
+Description : Yosys simulator implementation.
+Copyright : (c) Yann Herklotz Grave 2018
+License : GPL-3
+Maintainer : ymherklotz@gmail.com
+Stability : experimental
+Portability : POSIX
+
+Yosys simulator implementation.
+-}
+
+{-# LANGUAGE QuasiQuotes #-}
+
+module Test.VeriFuzz.Simulator.Yosys where
+
+import Data.Text (Text)
+import qualified Data.Text as T
+import Prelude hiding (FilePath)
+import Shelly
+import Test.VeriFuzz.Simulator.General
+import Test.VeriFuzz.Verilog.AST
+import Test.VeriFuzz.Verilog.CodeGen
+import Text.Shakespeare.Text (st)
+
+data Yosys = Yosys { yosysPath :: FilePath }
+
+instance Simulator Yosys where
+ toText _ = "yosys"
+
+instance Simulate Yosys where
+ runSim = runSimYosys
+
+instance Synthesize Yosys where
+ runSynth = runSynthYosys
+
+writeSimFile :: Yosys -- ^ Simulator instance
+ -> ModDecl -- ^ Current module
+ -> FilePath -- ^ Output sim file
+ -> Sh ()
+writeSimFile sim mod file = do
+ writefile "rtl.v" $ genSource mod
+ writefile file [st|read_verilog rtl.v; proc;;
+rename mod mod_rtl
+|]
+
+runSimYosys :: Yosys -> ModDecl -> [Int] -> Sh Int
+runSimYosys sim ver tb = return 0
+
+runSynthYosys :: Yosys -> ModDecl -> FilePath -> Sh ()
+runSynthYosys sim mod outf = do
+ writefile inpf $ genSource mod
+ run_ (yosysPath sim) ["-q", "-l", "synth.log", "-b", "verilog -noattr", "-o", out, "-S", inp]
+ where
+ inpf = "rtl.v"
+ inp = toTextIgnore inpf
+ out = toTextIgnore outf
generated by cgit (git 2.34.1) at 2024-07-01 09:41:47 +0000