diff options
-rw-r--r-- | src/Test/VeriFuzz.hs | 13 | ||||
-rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 6 | ||||
-rw-r--r-- | src/Test/VeriFuzz/Helpers.hs | 10 | ||||
-rw-r--r-- | tests/Unit.hs | 4 | ||||
-rw-r--r-- | verifuzz.cabal | 20 |
5 files changed, 29 insertions, 24 deletions
diff --git a/src/Test/VeriFuzz.hs b/src/Test/VeriFuzz.hs index 1a0b81b..8a84fd7 100644 --- a/src/Test/VeriFuzz.hs +++ b/src/Test/VeriFuzz.hs @@ -12,25 +12,22 @@ module Test.VeriFuzz ( -- * Definitions module Test.VeriFuzz.Circuit - -- * Code Generation - , module Test.VeriFuzz.CodeGen -- * Verilog AST Data Types - , module Test.VeriFuzz.VerilogAST - -- * AST Mutation - , module Test.VeriFuzz.Mutate + , module Test.VeriFuzz.Verilog -- * Helpers , module Test.VeriFuzz.Helpers -- * Graphs , module Test.VeriFuzz.Graph.ASTGen , module Test.VeriFuzz.Graph.CodeGen , module Test.VeriFuzz.Graph.Random + -- * Simulator + , module Test.VeriFuzz.Simulator ) where import Test.VeriFuzz.Circuit -import Test.VeriFuzz.CodeGen import Test.VeriFuzz.Graph.ASTGen import Test.VeriFuzz.Graph.CodeGen import Test.VeriFuzz.Graph.Random import Test.VeriFuzz.Helpers -import Test.VeriFuzz.Mutate -import Test.VeriFuzz.VerilogAST +import Test.VeriFuzz.Simulator +import Test.VeriFuzz.Verilog diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index f1ac88a..5382123 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -18,7 +18,7 @@ import Data.Maybe (catMaybes) import qualified Data.Text as T import Test.VeriFuzz.Circuit import Test.VeriFuzz.Internal.Gen -import Test.VeriFuzz.VerilogAST +import Test.VeriFuzz.Verilog.AST -- | Converts a 'Node' to an 'Identifier'. frNode :: Node -> Identifier @@ -73,5 +73,5 @@ genModuleDeclAST c = ModDecl id ports items ports = genPortsAST c items = genAssignAST c -generateAST :: Circuit -> SourceText -generateAST c = SourceText [Description $ genModuleDeclAST c] +generateAST :: Circuit -> VerilogSrc +generateAST c = VerilogSrc [Description $ genModuleDeclAST c] diff --git a/src/Test/VeriFuzz/Helpers.hs b/src/Test/VeriFuzz/Helpers.hs index 3650f8e..157e56c 100644 --- a/src/Test/VeriFuzz/Helpers.hs +++ b/src/Test/VeriFuzz/Helpers.hs @@ -13,9 +13,9 @@ Defaults and common functions. module Test.VeriFuzz.Helpers where import Control.Lens -import Data.Text (Text) +import Data.Text (Text) import qualified Data.Text -import Test.VeriFuzz.VerilogAST +import Test.VeriFuzz.Verilog.AST regDecl :: Text -> ModItem regDecl = Decl . Port Nothing (Just $ Reg False) . Identifier @@ -42,8 +42,8 @@ setModName str = moduleId .~ Identifier str addModPort :: Port -> ModDecl -> ModDecl addModPort port = modPorts %~ (:) port -addDescription :: Description -> SourceText -> SourceText -addDescription desc = getSourceText %~ (:) desc +addDescription :: Description -> VerilogSrc -> VerilogSrc +addDescription desc = getVerilogSrc %~ (:) desc testBench :: ModDecl testBench = @@ -69,5 +69,5 @@ testBench = ] ] -addTestBench :: SourceText -> SourceText +addTestBench :: VerilogSrc -> VerilogSrc addTestBench = addDescription $ Description testBench diff --git a/tests/Unit.hs b/tests/Unit.hs index 440953a..67f642c 100644 --- a/tests/Unit.hs +++ b/tests/Unit.hs @@ -43,7 +43,7 @@ runMain = do gr <- genRandomDAG 100 :: IO (G.Gr Gate ()) -- _ <- runGraphviz (graphToDot quickParams $ emap (const "") gr) Png "output.png", -- T.putStrLn $ generate gr - --g <- QC.generate (QC.arbitrary :: QC.Gen SourceText) + --g <- QC.generate (QC.arbitrary :: QC.Gen VerilogSrc) let x = generateAST $ Circuit gr - let y = head . reverse $ x ^.. getSourceText . traverse . getDescription . moduleItems . traverse . _ModCA . contAssignExpr + let y = head . reverse $ x ^.. getVerilogSrc . traverse . getDescription . moduleItems . traverse . _ModCA . contAssignExpr print $ transformOf traverseExpr trans y diff --git a/verifuzz.cabal b/verifuzz.cabal index e4e3c06..28838e0 100644 --- a/verifuzz.cabal +++ b/verifuzz.cabal @@ -20,19 +20,27 @@ library , Test.VeriFuzz.Internal.Gen exposed-modules: Test.VeriFuzz , Test.VeriFuzz.Circuit - , Test.VeriFuzz.CodeGen - , Test.VeriFuzz.Mutate - , Test.VeriFuzz.Helpers , Test.VeriFuzz.Graph.ASTGen , Test.VeriFuzz.Graph.CodeGen , Test.VeriFuzz.Graph.Random - , Test.VeriFuzz.VerilogAST + , Test.VeriFuzz.Helpers + , Test.VeriFuzz.Simulator + , Test.VeriFuzz.Simulator.General + , Test.VeriFuzz.Simulator.Icarus + , Test.VeriFuzz.Simulator.Xst + , Test.VeriFuzz.Simulator.Yosys + , Test.VeriFuzz.Verilog + , Test.VeriFuzz.Verilog.AST + , Test.VeriFuzz.Verilog.CodeGen + , Test.VeriFuzz.Verilog.Mutate build-depends: base >= 4.7 && < 5 , QuickCheck , fgl - , text - , random , lens + , random + , shakespeare + , shelly + , text extensions: OverloadedStrings executable yosys |