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-rw-r--r--src/Verismith/Verilog/Mutate.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Verismith/Verilog/Mutate.hs b/src/Verismith/Verilog/Mutate.hs
index 586e085..a4a188b 100644
--- a/src/Verismith/Verilog/Mutate.hs
+++ b/src/Verismith/Verilog/Mutate.hs
@@ -244,7 +244,7 @@ instantiateMod m main = main & modItems %~ ((out ++ regIn ++ [inst]) ++)
^.. modItems
. traverse
. modInstId
- conns = ModConn . Id <$> allVars m
+ conns = uncurry ModConnNamed . fmap Id <$> zip (allVars m) (allVars m)
-- | Instantiate without adding wire declarations. It also does not count the
-- current instantiations of the same module.