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-rw-r--r-- | README.md | 3 |
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@@ -1,2 +1,5 @@ +![Build Status](https://travis-ci.com/ymherklotz/verifuzz.svg?token=qfBKKGwxeWkjDsy7e16x&branch=master) + # verifuzz + Verilog Fuzzer to test the major verilog compilers by generating random, valid verilog. |