diff options
-rw-r--r-- | src/VeriFuzz.hs | 3 | ||||
-rw-r--r-- | src/VeriFuzz/Fuzz.hs | 7 | ||||
-rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 17 |
3 files changed, 13 insertions, 14 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs index cd6596c..d40fdaf 100644 --- a/src/VeriFuzz.hs +++ b/src/VeriFuzz.hs @@ -137,7 +137,7 @@ checkEquivalence src dir = shellyFailDir $ do cd (fromText dir) catch_sh ( ( runResultT - $ runEquiv defaultYosys defaultYosys (Just defaultVivado) src + $ runEquiv defaultYosys (Just defaultVivado) src ) >> return True ) @@ -166,7 +166,6 @@ runEquivalence seed gm t d k i = do catch_sh ( runResultT $ runEquiv defaultYosys - defaultYosys (Just defaultVivado) srcInfo >> liftSh (logger "Test OK") diff --git a/src/VeriFuzz/Fuzz.hs b/src/VeriFuzz/Fuzz.hs index c1bbfe4..7390aee 100644 --- a/src/VeriFuzz/Fuzz.hs +++ b/src/VeriFuzz/Fuzz.hs @@ -138,15 +138,14 @@ pop f a = do equivalence :: (MonadBaseControl IO m, MonadSh m) => SourceInfo -> Fuzz m () equivalence src = do - yos <- lift $ asks yosysInstance synth <- passedSynthesis let synthComb = nubBy tupEq . filter (uncurry (/=)) $ combinations synth synth - results <- liftSh $ mapM (uncurry $ equiv yos) synthComb + results <- liftSh $ mapM (uncurry equiv) synthComb liftSh $ inspect results where tupEq (a, b) (a', b') = (a == a' && b == b') || (a == b' && b == a') - equiv yos a b = runResultT $ do + equiv a b = runResultT $ do make dir pop dir $ do liftSh $ do @@ -155,7 +154,7 @@ equivalence src = do cp (fromText ".." </> fromText (toText b) </> synthOutput b) $ synthOutput b writefile "rtl.v" $ genSource src - runEquiv yos a (Just b) src + runEquiv a (Just b) src where dir = fromText $ "equiv_" <> toText a <> "_" <> toText b fuzz :: MonadFuzz m => Gen SourceInfo -> Config -> Fuzz m FuzzReport diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 656bc52..50c9759 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -21,6 +21,7 @@ module VeriFuzz.Sim.Yosys where import Control.Lens +import Data.Text import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) @@ -31,24 +32,25 @@ import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Mutate -data Yosys = Yosys { yosysPath :: {-# UNPACK #-} !FilePath - , yosysOutput :: {-# UNPACK #-} !FilePath +data Yosys = Yosys { yosysPath :: {-# UNPACK #-} !FilePath + , yosysDescription :: {-# UNPACK #-} !Text + , yosysOutput :: {-# UNPACK #-} !FilePath } deriving (Eq) instance Tool Yosys where - toText _ = "yosys" + toText (Yosys _ t _) = t instance Synthesiser Yosys where runSynth = runSynthYosys synthOutput = yosysOutput - setSynthOutput (Yosys a _) = Yosys a + setSynthOutput (Yosys a b _) = Yosys a b instance Show Yosys where show _ = "yosys" defaultYosys :: Yosys -defaultYosys = Yosys "yosys" "syn_yosys.v" +defaultYosys = Yosys "yosys" "syn_yosys.v" "yosys" runSynthYosys :: Yosys -> SourceInfo -> ResultSh () runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do @@ -98,12 +100,11 @@ runEquivYosys yosys sim1 sim2 srcInfo = do runEquiv :: (Synthesiser a, Synthesiser b) - => Yosys - -> a + => a -> Maybe b -> SourceInfo -> ResultSh () -runEquiv _ sim1 sim2 srcInfo = do +runEquiv sim1 sim2 srcInfo = do dir <- liftSh pwd liftSh $ do writefile "top.v" |