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| -rw-r--r-- | src/Verismith/Tool/Template.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/Verismith/Tool/Template.hs b/src/Verismith/Tool/Template.hs index 56a35e5..5402702 100644 --- a/src/Verismith/Tool/Template.hs +++ b/src/Verismith/Tool/Template.hs @@ -120,6 +120,7 @@ sbyConfig :: (Synthesiser a, Synthesiser b) => FilePath -> a -> b -> SourceInfo sbyConfig datadir sim1 sim2 (SourceInfo top _) = [st|[options] multiclock on mode prove +aigsmt z3 [engines] abc pdr |