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-rw-r--r--app/Simulation.hs3
1 files changed, 2 insertions, 1 deletions
diff --git a/app/Simulation.hs b/app/Simulation.hs
index 675a7dc..28950c2 100644
--- a/app/Simulation.hs
+++ b/app/Simulation.hs
@@ -55,7 +55,8 @@ runSimulation = do
let circ =
head $ (nestUpTo 30 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription
rand <- genRandom 20
- val <- shelly $ runSim defaultIcarus (initMod circ) rand
+ rand2 <- QC.generate (randomMod 10 100)
+ val <- shelly $ runSim defaultIcarus (rand2) rand
T.putStrLn . decodeUtf8 $ (L.toStrict . toLazyByteString . byteStringHex $ val)
onFailure :: Text -> RunFailed -> Sh ()