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@@ -3,14 +3,17 @@ Verilog Fuzzer to test the major verilog compilers by generating random, valid verilog. -It currently supports the following simulators: +It currently supports the following synthesisers: - [Yosys](http://www.clifford.at/yosys/) -- [Icarus Verilog](http://iverilog.icarus.com) - [Xst](https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_xst_for_synthesis.htm) - [Vivado](https://www.xilinx.com/products/design-tools/ise-design-suite.html) - [Quartus](https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html) +and the following simulator: + +- [Icarus Verilog](http://iverilog.icarus.com) + ## Build the Fuzzer The fuzzer is split into an executable (in the [app](/app) folder) and a |