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feature/ignored-constructs
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Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
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Setup.hs
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-rw-r--r--
Setup.hs
2
1 files changed, 1 insertions, 1 deletions
diff --git a/Setup.hs b/Setup.hs
index 9a994af..4467109 100644
--- a/
Setup.hs
+++ b/
Setup.hs
@@ -1,2 +1,2 @@
-import Distribution.Simple
+import Distribution.Simple
main = defaultMain