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-rw-r--r--app/Main.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/app/Main.hs b/app/Main.hs
index 2e90b37..efa61e6 100644
--- a/app/Main.hs
+++ b/app/Main.hs
@@ -38,7 +38,7 @@ runSimulation = do
let circ = head $ (nestUpTo 5 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription
rand <- genRandom 20
val <- shelly $ runSim defaultIcarus (initMod circ) rand
- putStrLn $ showHex val ""
+ putStrLn $ showHex (abs val) ""
runEquivalence:: IO ()
runEquivalence = do