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Diffstat (limited to 'src/Test/VeriFuzz/Graph/ASTGen.hs')
| -rw-r--r-- | src/Test/VeriFuzz/Graph/ASTGen.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Graph/ASTGen.hs b/src/Test/VeriFuzz/Graph/ASTGen.hs index cf996de..3c000ea 100644 --- a/src/Test/VeriFuzz/Graph/ASTGen.hs +++ b/src/Test/VeriFuzz/Graph/ASTGen.hs @@ -77,7 +77,7 @@ genModuleDeclAST c = ModDecl id output ports items where id = Identifier "gen_module" ports = genPortsAST inputsC c - output = Just $ Port (PortNet Wire) 1 "y" + output = [Port (PortNet Wire) 1 "y"] items = genAssignAST c generateAST :: Circuit -> VerilogSrc |