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-rw-r--r--src/Test/VeriFuzz/Verilog/AST.hs12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/Test/VeriFuzz/Verilog/AST.hs b/src/Test/VeriFuzz/Verilog/AST.hs
index 8a4692e..5fa2d51 100644
--- a/src/Test/VeriFuzz/Verilog/AST.hs
+++ b/src/Test/VeriFuzz/Verilog/AST.hs
@@ -143,11 +143,13 @@ instance Num Expr where
fromInteger = Number 32 . fromInteger
instance Semigroup Expr where
- a <> b = mconcat [a, b]
+ (Concat a) <> (Concat b) = Concat $ a <> b
+ (Concat a) <> b = Concat $ a <> [b]
+ a <> (Concat b) = Concat $ a : b
+ a <> b = Concat [a, b]
instance Monoid Expr where
mempty = 0
- mconcat = Concat
instance IsString Expr where
fromString = Str . fromString
@@ -224,11 +226,13 @@ data Stmnt = TimeCtrl { _statDelay :: Delay
deriving (Eq)
instance Semigroup Stmnt where
- a <> b = mconcat [a, b]
+ (SeqBlock a) <> (SeqBlock b) = SeqBlock $ a <> b
+ (SeqBlock a) <> b = SeqBlock $ a <> [b]
+ a <> (SeqBlock b) = SeqBlock $ a : b
+ a <> b = SeqBlock [a, b]
instance Monoid Stmnt where
mempty = EmptyStat
- mconcat = SeqBlock
data Task = Task { _taskName :: Identifier
, _taskExpr :: [Expr]