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-rw-r--r--src/Test/VeriFuzz/Verilog/CodeGen.hs2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Test/VeriFuzz/Verilog/CodeGen.hs b/src/Test/VeriFuzz/Verilog/CodeGen.hs
index e1114d2..7861294 100644
--- a/src/Test/VeriFuzz/Verilog/CodeGen.hs
+++ b/src/Test/VeriFuzz/Verilog/CodeGen.hs
@@ -47,7 +47,7 @@ genModuleDecl mod =
where
ports
| noIn && noOut = ""
- | otherwise = "(" <> out <> (sep ", " $ genModPort <$> mod ^. modInPorts) <> ")"
+ | otherwise = "(" <> out <> (sep_ ", " $ genModPort <$> mod ^. modInPorts) <> ")"
modItems = fromList $ genModuleItem <$> mod ^. moduleItems
noOut = isNothing $ mod ^. modOutPort
noIn = null $ mod ^. modInPorts