aboutsummaryrefslogtreecommitdiffstats
path: root/src/Test/VeriFuzz/Verilog/Helpers.hs
diff options
context:
space:
mode:
Diffstat (limited to 'src/Test/VeriFuzz/Verilog/Helpers.hs')
-rw-r--r--src/Test/VeriFuzz/Verilog/Helpers.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Test/VeriFuzz/Verilog/Helpers.hs b/src/Test/VeriFuzz/Verilog/Helpers.hs
index 4410532..6712d32 100644
--- a/src/Test/VeriFuzz/Verilog/Helpers.hs
+++ b/src/Test/VeriFuzz/Verilog/Helpers.hs
@@ -32,7 +32,7 @@ numExpr = ((PrimExpr . PrimNum) .) . Number
-- | Create an empty module.
emptyMod :: ModDecl
-emptyMod = ModDecl "" Nothing [] []
+emptyMod = ModDecl "" [] [] []
-- | Set a module name for a module declaration.
setModName :: Text -> ModDecl -> ModDecl
@@ -47,7 +47,7 @@ addDescription desc = getVerilogSrc %~ (:) desc
testBench :: ModDecl
testBench =
- ModDecl "main" Nothing []
+ ModDecl "main" [] []
[ regDecl "a"
, regDecl "b"
, wireDecl "c"