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-rw-r--r--src/VeriFuzz/CodeGen.hs12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/VeriFuzz/CodeGen.hs b/src/VeriFuzz/CodeGen.hs
index f35eff7..3e36cf5 100644
--- a/src/VeriFuzz/CodeGen.hs
+++ b/src/VeriFuzz/CodeGen.hs
@@ -68,12 +68,17 @@ genModPort port = port ^. portName . getIdentifier
-- | Generate the 'Port' description.
genPort :: Port -> Text
-genPort port = t <> size <> name
+genPort port = t <> sign <> size <> name
where
- t = (<> " ") . genPortType $ port ^. portType
+ t = flip mappend " " . genPortType $ port ^. portType
size | port ^. portSize > 1 = "[" <> showT (port ^. portSize - 1) <> ":0] "
| otherwise = ""
name = port ^. portName . getIdentifier
+ sign = genSigned $ port ^. portSigned
+
+genSigned :: Bool -> Text
+genSigned True = "signed "
+genSigned _ = ""
-- | Convert the 'PortDir' type to 'Text'.
genPortDir :: PortDir -> Text
@@ -188,8 +193,7 @@ genConstExpr (ConstExpr num) = showT num
genPortType :: PortType -> Text
genPortType Wire = "wire"
-genPortType (Reg signed) | signed = "reg signed"
- | otherwise = "reg"
+genPortType Reg = "reg"
genAssign :: Text -> Assign -> Text
genAssign op (Assign r d e) = genLVal r <> op <> maybe "" genDelay d <> genExpr e